1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device, and more particularly to a multilayer-wiring structure with polycrystalline silicon which is capable of increasing the integration density.
2. Description of the Prior Art
In recent MOS integrated circuit devices, miniaturization of elements has become so advanced that pattern dimensions are approaching the micron or submicron range. One of the most important problems in the miniaturization of the elements lies in the formation of a micro-pattern by the photolithographic method. Even a miniature pattern with a size of one micron is going to be in practical use.
Meanwhile, the design of multilayer structures is progressing along with a tendency toward high density semiconductor integrated circuit devices. An important factor in the multilayer structure is improvement of the superposition accuracy. However, the fact that this accuracy depends strongly on the mechanical accuracy of an exposure apparatus has retarded an increase in the integration density.